Operator Library: Hardware Platform
The DmaToPC operator is the image interface between a VisualApplets applet and the host PC. The DMAToPC operator transfers images from the applet to the host PC. Image transfer is performed using direct memory access, i.e., the image data is directly written to the host PC memory.
The operator uses one VisualApplets resource of type DMA. Set the resource index for the DMA in the resource dialog. Depending on the used frame grabber, multiple DMA channels can be used. Check 'Allocation of Device Resources' for more information.
Multitple color formats, bit widths and parallelisms are supported. The allowed combinations depend on the used hardware platform:
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imaFlex CXP-12 Quad:
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The product of the bit width and parallelism must be an integer multiple of 8 and must be less than or equal to 256.
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The product of the maximal image width and the maximal image height must be divisible by 4 bytes.
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microEnable 5 marathon VCLx, microEnable 5 marathon VCL, microEnable 5 marathon VCX-QP, microEnable 5 marathon VF2, and LightBridge VCL:
The link properties of the operator input depend on the PCIe mode that is supported by the applet. The supported PCIe mode you can select in operator AppletProperties, parameter PcieInterfaceType.
Multiple color formats, bit widths and parallelism are supported. The maximum of the product Parallelism x Bit Width must be a multiple of 8 and depends on the PCIe mode you selected in operator AppletProperties:
- Generation_1: Parallelism x Bit Width <= 64 Bit.
- Generation_2: Parallelism x Bit Width <= 128 bit
The product of the maximal image width and the maximal image height must be divisible by 4 bytes.
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microEnable 5 ironman VD8-PoCL, microEnable 5 ironman VQ8-CXP6D (DIN connector) and microEnable 5 ironman VQ8-CXP6B (BNC connector):
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When parameter PcieInterfaceType in the operator AppletProperties is set to Generation_1, the product of the bit width and the parallelism must be a multiple of 8 and less or equal to 128.
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When parameter PcieInterfaceType in the operator AppletProperties is set to Generation_2, the product of the bit width and the parallelism must be a multiple of 8 and less or equal to 256.
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microEnable IV VD4-CL/-PoCL and microEnable IV VQ4-GE/-GPoE:
For the frame grabbers using a PCIe x4 interface, the product of the bit width and parallelism must be an integer multiple of 8 and must be less than or equal to 128.
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microEnable IV VD1-CL/-PoCL:
For grayscale images, the product of the parallelism and bit width must either be 16, 32, 64 or 128. In case of color formats, the product either has to be 24 or 48.
![[Note]](../common/images/admon/note.png) |
RGB is converted to BGR |
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The operator converts RGB data to BGR data (i.e., the components R and B are switched before DMA transfer). After DMA transfer, the former RGB image is available as a BGR image in the PC's RAM. This conversion is carried out to ease further processing with software tools, as most software tools directly support BGR format. |
| Available for Hardware Platforms |
|---|
| imaFlex CXP-12 Quad |
| microEnable 5 marathon VCLx |
| microEnable 5 marathon VCL |
| microEnable 5 marathon VCX-QP |
| microEnable 5 marathon VF2 |
| LightBridge VCL |
| microEnable 5 ironman VQ8-CXP6D/-CXP6B |
| microEnable 5 ironman VD8-PoCL |
| microEnable IV VD1-CL/-PoCL |
| microEnable IV VD4-CL/-PoCL |
| microEnable IV VQ4-GE/-GPoE |
| Link Parameter | Input Link I |
|---|---|
| Bit Width | see description |
| Arithmetic | unsigned |
| Parallelism | see description |
| Kernel Columns | 1 |
| Kernel Rows | 1 |
| Img Protocol | VALT_IMAGE2D |
| Color Format | {VAF_COLOR, VAF_GRAY} |
| Color Flavor | {FL_NONE, FL_RGB} If VAF_GRAY selected: FL_NONE; If VAF_COLOR selected: FL_RGB |
| Max. Img Width | any |
| Max. Img Height | any |
| CurrentTransferLength | ||||
|---|---|---|---|---|
| Type | dynamic read parameter | |||
| Default | ||||
| Range | [0; 2^34-1] | |||
|
The parameter reflects the amount of byte that has already been transferred of a frame that is being processed. This information allows to analyze DMA buffer data in a software application before the entire frame is transmitted.
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| PixelsPerLine | ||||
|---|---|---|---|---|
| Type | dynamic read parameter | |||
| Default | 0 | |||
| Range | ||||
|
The previously transferred image line length in pixels.
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| PixelsPerLine | ||||
|---|---|---|---|---|
| Type | dynamic read parameter | |||
| Default | 0 | |||
| Range | ||||
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The previously transferred image line length in bytes.
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| ReadLongsPerLine | ||||
|---|---|---|---|---|
| Type | dynamic read parameter | |||
| Default | 0 | |||
| Range | ||||
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This parameter provides the geometry of the transferred frame. The number of long words (4 byte) per line can be read.
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The use of operator DmaToPC is shown in the following examples:
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Getting Started
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Figure 9, 'Simple VisualApplets Design'
Basic Principles - Learn the Idea of VisualApplets
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Data Flow - Learn about the Pipeline Structure used in VisualApplets
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'Allocation of Device Resources'
Learn the allocation of the device resources of the operator.
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' Multiple DMA Channel Designs '
Tutorial - Using multiple DMA channel outputs for one camera.
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Examples - A simple example which shows the usage of the JPEG operators.
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'JPEG Compression Using Operator JPEG_Encoder'
Examples - Simple examples which show the usage of the operator JPEG_Encoder.
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'JPEG Color Compression Using User Library Elements'
Examples - Simple examples which shows the usage of the JPEG user library elements for color JPEG compression.
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Examples - A high speed and robust laser line detection algorithm. The algorithm determines center of gravity coordinates to obtain sub-pixel resolution results.
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'Color Plane Separation Option 1 - Three DMAs'
Splitting the RGB color planes into three DMA channel outputs.
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Examples - The coprocessor feature of the microEnable IV VD1-CL is shown. As an example, a median filter is calculated.
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'Co-Processor Large Filter Calculation'
Examples - The coprocessor feature of the microEnable IV VD1-CL is shown. As an example, a large filter kernel is calculated.
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Example - For debugging purposes of the designs internal data flow control in hardware and a possible compensation.
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